Avery Dennison Press Release:

Avery Dennison to Sponsor Emerging Fashion Brand Award at WGSN Global Fashion Awards 2013

Emerging Designer will Receive €12,000 in Funding to Build Collection Brand

Thursday, May 30, 2013 3:00 am PDT

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LONDON--(BUSINESS WIRE)--Avery Dennison Retail Branding and Information Solutions (AD/RBIS) the world’s leading apparel branding solutions provider will sponsor the WGSN Global Fashion Awards, including offering a new award in support of emerging apparel designers and the successful development of their independent fashion brand. The Avery Dennison Emerging Fashion Brand Award will not only give these rising talents the opportunity to showcase their work in front of an international jury of 50 prominent fashion designers, opinion leaders and journalists, but will also fund €12,000 to help the winners further develop their brand.

A global leader in apparel branding solutions, Avery Dennison empowers designers with the latest innovative product branding solutions which enable design creativity, brand integrity, and ultimately the ability to tell a compelling brand story. With these solutions, Avery Dennison works with leading global apparel brands to enable designers to create high-impact brand graphics and distinctive finishing touches as part of a garment’s design.

Branding is essential to the appeal of a garment to the consumer and the success of any apparel company, and the more integral branding becomes to the apparel design process, the more effectively a company can communicate its brand values. This is why Avery Dennison has challenged the WGSN finalists to unleash their creativity and create an inspiring brand story for their collection by considering the conceptual application of the company’s full complement of branding solutions and tools – from woven and printed labels, to standout heat transfer embellishments, and sustainable hangtags and packaging solutions.

To qualify for the awards, brands or designers must have their own independent label, which should be no more than two years old as of 30 June 2013. Entries are welcome from around the world; however, the award is not open to currently enrolled students. The best submissions will also benefit from being posted on Arts Thread™, the only creative graduate website which aims to promote new talent on a global scale. Through their partnership with Arts Thread, Avery Dennison and WGSN will increase visibility of the award among the emerging designer community.

Judges will consider not only the independent designer’s collection branding but also his or her collective brand vision, from the website through to their marketing. The brand with the most coherent and creative vision will win the award.

“Converting hard-earned recognition on the catwalk into building a successful brand is the biggest challenge facing every designer,” says Tim Voegele-Downing, global creative director, Avery Dennison RBIS. “We are looking for a designer who is not only capable of creating an inspired fashion collection, but who also truly understands the importance of product branding and is capable of telling a compelling brand story.”
Lauretta Roberts, WGSN Global Fashion Awards director, says: “Avery Dennison is a leading expert in apparel branding, something that is key to success in modern retail. Together we’re looking for someone we believe has a long future in fashion demonstrated by the vision they have for their brand.”

“We work on a regular basis with design teams from some of the world’s largest apparel brands, and we are excited to partner with WGSN and Arts Thread to bring our insights to emerging designers and help them understand the importance of product branding in realizing their vision,” said Tracy Van Hoven, vice president, global marketing communications, Avery Dennison RBIS. “Branding is such a vital part of the fashion industry, and we are excited to see how these talented designers integrate our unique branding solutions into their collection and their marketing vision to effectively compete.”

The Awards take place on October 30, 2013 in London. Entries for the award are now open at www.globalfashionawards.com/categories with a closing of Wednesday, June 12th.
Judges for this year’s WGSN Global Fashion Awards include designers Giles Deacon, Bora Aksu, Stephen Jones and Rebecca Minkoff, model and writer Laura Bailey, Eco-Age founder Livia Firth, blogger Bip Ling, singers VV Brown and Kate Nash, Tim Voegele-Downing, and Mr Porter editor-in-chief Jeremy Langmead.

About Avery Dennison RBIS
Avery Dennison RBIS, a global leader in apparel and footwear industry solutions, is a $1.5 billion division of Avery Dennison (NYSE: AVY). Avery Dennison RBIS provides intelligent, creative and sustainable solutions to elevate brands and accelerate performance from design to retail store floor. The company’s industry leading, end‐to‐end solutions include innovative heat transfer technology, RFID and price management supply chain solutions and sustainable packaging services. Based in Framingham, Massachusetts, Avery Dennison RBIS has 115 locations in 50 countries and across six continents. For more information, visit www.rbis.averydennison.com.

About Avery Dennison
Avery Dennison (NYSE:AVY) is a global leader in labelling and packaging materials and solutions. The company’s applications and technologies are an integral part of products used in every major market and industry. With operations in more than 50 countries and 30,000 employees worldwide, Avery Dennison serves customers with insights and innovations that help make brands more inspiring and the world more intelligent. Headquartered in Pasadena, California, the company reported sales from continuing operations of $6 billion in 2012. Learn more at www.averydennison.com.     

Synopsys Announces DesignWare DDR4 Memory Interface IP

News release:

Synopsys Announces DesignWare DDR4 Memory Interface IP

Memory Controller and PHY Support Multiple DDR Standards While Reducing Latency and Standby Power

MOUNTAIN VIEW, Calif., Sept. 18, 2012 /PRNewswire/ --
Highlights:

• Synopsys expands its industry-leading DesignWare® DDR Memory Interface IP family to include support for DDR4 SDRAMs
• Backward compatibility with DDR3 and LPDDR2/3 mobile SDRAMs gives SoC designers flexibility as they transition from one SDRAM standard to the next
• New DDR4 IP offers more features with up to 50 percent lower latency than the previous generation
• DDR4 memory controller and PHY are connected by a standard DFI 3.1 interface to streamline connections to custom PHYs and controllers

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the emerging DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.
"Synopsys' support for DDR4 memory is an important contribution to building a robust DDR4 ecosystem," said Robert Feurle, vice president of DRAM marketing for Micron Technology, Inc. "DDR4 brings substantial power and performance benefits to the industry, and Micron is aggressively driving its introduction. By implementing their DesignWare DDR Interface IP with backward compatibility in mind, Synopsys is enabling chip developers to bridge the transition from today's DDR3-based SoCs to the upcoming DDR4 designs."
Synopsys' DesignWare DDR4 IP solution consists of the DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface. The new DDR4 IP supports all key DDR4 features planned for the upcoming JEDEC standard and, compared to the previous version, includes a 13 percent increase in raw bandwidth, up to a 50 percent reduction in overall latency and new low-power features that provide intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns. Real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance and minimizing latency.
"While the initial target markets for DDR4 are networking, server, and compute platforms, engineers designing for digital TVs, set-top-boxes, multi-function printing, smartphone and tablet applications will also adopt DDR4 DRAM as prices drop and performance improves," said Desi Rhoden, executive vice president, Montage Technology, and JEDEC memory chairman. "Synopsys has leveraged their participation at JEDEC to develop DDR4-compatible products before the actual standard has been released, which is a key benefit of JEDEC membership."
"Synopsys' complete DDR interface IP portfolio includes support for LPDDR, LPDDR2, LPDDR3, DDR, DDR2, and DDR3," said John Koeter, vice president of marketing for IP and systems at Synopsys. "With this announcement, we are broadening our portfolio to include support for DDR4 while maintaining backward compatibility with existing JEDEC standard SDRAMs. As new DDR standards evolve, designers look for reliable solutions. Synopsys' track record of over 320 DDR IP design wins demonstrates that we offer a low-risk path to silicon success."
Availability
Availability for the DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4 is planned for Q4 2012.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for system-on-chip (SoC) designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer™ virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
Forward Looking Statements
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected availability of Synopsys' DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, unforeseen production or delivery delays, failure to perform as expected, product errors or defects and other risks detailed in Synopsys' filings with the U.S. Securities and Exchange Commission, including those described in the "Risk Factors" section of Synopsys' Quarterly Report on Form 10-Q for the fiscal quarter ended July 31, 2012.

Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance For 20nm and Below

Press release:

Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance For 20nm and Below

Advances Include Faster Runtime, ECO Flows and New Process Modeling Technology

MOUNTAIN VIEW, Calif., Sept. 6, 2012 /PRNewswire/ --
Highlights:

• Qualified by leading foundries for 20 nanometers (nm)
• Successful in numerous tapeouts targeted for 20nm
• Introduces new double patterning (DPT) decomposition checking and pattern matching technologies for optimal compliance with foundry manufacturing requirements 
• Enables reduced verification turnaround time with demonstrated scalability to 64 cores and beyond
• Expands In-Design technology for automatic DRC/DPT repair and 2X faster ECOs

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the release of IC Validator 2012.06, Synopsys' physical verification platform for advanced process nodes. With immediate availability of qualified rule decks by leading foundries, IC Validator 2012.06 offers new technologies that enable physical signoff verification at advanced process nodes. IC Validator 2012.06 continues to build on Synopsys' approach of speeding design closure through In-Design physical verification with Synopsys' IC Compiler^™ place and route solution, enabling place-and-route engineers to eliminate late stage surprises and manual repairs. New additions to the In-Design flow, targeted for 20nm and below, include DPT and pattern matching technology. This latest release of IC Validator also offers a significant performance boost for verifying large and complex 20-nm designs. By maximizing the utilization of mainstream computing hardware through innovative techniques, IC Validator can enable engineers to parallelize design rule checks (DRCs) on 64 processing cores and beyond, thereby significantly reducing verification turnaround time for these advanced process nodes.
"To address the complexities of 20nm process, we are actively expanding the use of In-Design Physical verification with IC Compiler and IC Validator for our new designs," said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics.
Enabling Physical Verification at 20nm and BelowTo address the stringent manufacturing requirements of 20-nm design, IC Validator 2012.06 introduces several new advances in process modeling technology:

• Double Patterning: The limitations of current lithographic technology require layout to be split into two masks of alternating structures. IC Validator features a fast and accurate, native decomposition ("coloring") engine. IC Validator can perform decomposition checks during design and can also drive automatic fixing of violations with IC Compiler via the In-Design technology. IC Validator can also perform the final signoff quality check alongside the final design rule check.
• Pattern Matching: Occasionally layout patterns can generate lithography hotspots, leading to accidental open or short connections. IC Validator's patented pattern-matching technology augments DRC with intuitive 2D multi-shape pattern analysis for ultra-fast detection of manufacturing hotspots. It can also drive automatic fixing of these hotspots with IC Compiler. Leading manufacturers will thus be able to achieve better process margins and higher yields for the 20-nm process node.

Improving Design Turnaround TimeIC Validator is being broadly used by design teams for In-Design physical verification with IC Compiler. This release complements IC Compiler 2012.06, allowing users to benefit from 2X faster ECO and automatic design repair (ADR) flows. New additions to In-Design technology also make it possible for designers to perform layout enhancement for yield natively within IC Compiler, streamlining the design flow and eliminating wasteful iterations.
In addition to being used for In-Design verification, IC Validator is also fully qualified for physical signoff at leading foundries across a broad range of process technologies. IC Validator 2012.06 deploys a range of distributed multiprocessing techniques to achieve optimal utilization of available hardware. These technologies, including multi-threading, on-demand load balancing and memory-aware scheduling, have demonstrated scalability to 64 cores and beyond. With this release, customers designing at advanced process nodes can now benefit from a significant productivity boost and faster turnaround times.
"IC Validator 2012.06 is the most noteworthy release for our physical verification product line to date," said Antun Domic, senior vice president and general manager of Synopsys' implementation group. "Beyond enabling verification of the highly complex 20-nanometer process technology node at Samsung and other leading foundries with a multitude of new technologies, we have added significant improvements in runtime, scalability and In-Design productivity that will benefit our entire customer base."
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Synopsys' RSoft OptSim Accelerates Design of Next-Generation Optical Communication Systems

Press release:

Synopsys' RSoft OptSim Accelerates Design of Next-Generation Optical Communication Systems

OptSim version 5.3 is now generally available

MOUNTAIN VIEW, Calif., Sept. 6, 2012 /PRNewswire/ --
Highlights:

• Expands support for modulation formats used in next-generation optical networks
• Accelerates design development with an expanded model library
• Speeds evaluation of optical signal propagation in data communication systems
• Increases user productivity with application examples

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the availability of the latest release of its RSoft™ Optical Communication Design Suite, which includes OptSim™ and its multimode companion tool ModeSYS™. OptSim version 5.3 delivers innovative modeling capabilities and new application examples that enable engineers to accelerate the design of high-performance optical communication systems.
"Optimized design of existing data links and the advancement of complex future designs can only be achieved with a thorough understanding of the underlying physics and technology involved, as well as the ability to predict performance and recognize design limitations," said Chris Kocot, principal scientist, Finisar Corporation. "At Finisar, simulation software is a crucial facilitator in this process. OptSim is a key component in our suite of software simulation tools used for advanced product development, including 28 Gb/s optical interconnects and next-generation optical links operating at 56 Gb/s per channel, as well as for high-speed link simulations that involve advanced modulation techniques."
Support for Cutting-Edge Modulation FormatsOptSim now includes models for accurately simulating coherent polarization-multiplexed binary phase-shift keying (PM-BPSK) as well as coherent multi-level polarization-multiplexed modulation formats such as PM-16QAM and PM-64QAM. These enhancements can help speed development of advanced applications such as single-carrier 100G Ethernet. The software also supports enhanced orthogonal frequency-division multiplexing (OFDM) models that can handle negative frequencies and calculate error vector magnitudes. This provides engineers with increased flexibility and power when developing OFDM-based systems, such as high-speed long-haul transmission systems with high inter-symbolic interference (ISI).
Application-Specific Models Accelerate Design DevelopmentOptSim now offers the following additions to its model library, which users can incorporate into their designs to jumpstart analysis of a wide range of systems, including photonic integrated circuits, long-reach and ultra-long-reach metro networks, and optical transport networks:

• Y-fed balanced-bridge dual-arm Mach-Zehnder modulator model
• Electrical filter synthesis based on data in Touchstone files
• Model of clipping in the electrical domain
• Phenomenological model for more easily implementing dispersion compensation

"OptSim has been a useful tool, giving us the ability to assess the performance of new systems before components are available for lab testing," said Steven Searcy, optical systems engineer, ADVA Optical Networking. "The ability to obtain preliminary design rules via simulation is critical to staying ahead in the development and introduction of new technologies."
Enhanced Multimode Fiber Modeling Speeds Evaluation of Optical Signal PropagationModeSYS includes an updated and enhanced multimode fiber model that provides faster calculation of mode-coupling equations. This can significantly accelerate evaluation of optical signal propagation in data communication systems.
Application Examples Increase User ProductivityNew application notes in OptSim demonstrate state-of-the-art examples that can reduce training time for new users and increase efficiency for experienced users. Application [examples] include polarization-multiplexed modulation formats, parametric fiber amplifiers, microwave photonics and multimode systems:

• PM-QPSK modulation using an external local oscillator
• Dual carrier PM-QPSK modulation
• In-band crosstalk in partial DPSK systems
• Phase-sensitive fiber parametric amplifiers
• Microwave photonic links based on balanced detection
• DMD test and measurement per IEC specification 60793-1-49
• EMB test and measurement per IEC specification 60793-1-41
• 25-Gbps directly modulated VCSEL-based multimode links

"OptSim 5.3 adds modeling enhancements that strengthen its standing as an ideal tool for optical communication design and simulation," said George Bayz, vice president and general manager of the Optical Solutions Group at Synopsys. "These new features are augmented by our continued focus on improving user productivity, with an expanded model library and detailed application notes. Our goal is to help engineers develop, test and deliver new systems more efficiently than ever."
Availability & ResourcesOptSim version 5.3 is available now and can be obtained by emailing rsoft_sales@synopsys.com. Learn more about Synopsys' RSoft products at http://www.synopsys.com/Tools/OpticalDesign.
About Synopsys' RSoft ProductsSynopsys' RSoft products are leading solutions in photonic design software and serve several industries including optical communications, optoelectronics and semiconductor manufacturing. RSoft products provide a full range of design, optimization and planning tools for optical communications, as well as solutions for optoelectronics components and subsystems.
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Synopsys' Open-Source Liberty Format to Incorporate On-Chip Variation Extensions

Press release:

Synopsys' Open-Source Liberty Format to Incorporate On-Chip Variation Extensions

Collaborating with Standards Board Industry Leaders to Ensure Broad Ecosystem Enablement

MOUNTAIN VIEW, Calif., Sept. 5, 2012 /PRNewswire/ --
Highlights:

• OCV extensions help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm
• Liberty Technical Advisory Board expected to finalize and ratify new extensions in November 2012

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced it intends to incorporate on-chip variation (OCV) extensions in its open-source Liberty™ library format, the de-facto modeling standard  for integrated circuit (IC) implementation and signoff. The new extensions will help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm processes nodes. The final format extensions and ratification as part of the Liberty standard will be completed with the guidance and assistance of the Liberty Technical Advisory Board.
The Liberty library format is the semiconductor industry's most widely adopted library standard used by virtually all EDA implementation, analysis and library characterization tools as the library model exchange for timing, noise, power and test behavior.  In May 2006, an industry-wide Liberty Technical Advisory Board was formed to facilitate the evolution of the Liberty library modeling standard. The Liberty Technical Advisory Board functions under the auspices of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). Its 14 member companies represent the broad semiconductor industry including the design community, EDA companies, silicon foundries, and semiconductor intellectual property (IP) companies. A complete list of members can be found at http://opensourceliberty.org/liberty_techadvisory.html. Liberty is available for download to the entire semiconductor design community under standard open-source terms. The latest Liberty syntax specifications and tools can be found at http://www.opensourceliberty.org.
"Standardizing the Liberty format extensions through the Liberty Technical Advisory Board allows the design community and EDA tool suppliers an opportunity to contribute and participate in the standardization process," said Rich Goldman, vice president of corporate marketing and strategic alliances, Synopsys. "In the past 2 years, the Liberty Technical Advisory Board has helped guide the ratification of over 10 new additions to Liberty to improve design for low-power flows."
The standardization of on-chip variation extensions via the Liberty Technical Advisory Board will benefit the semiconductor industry by:

• Allowing broad participation from the design community and EDA tool suppliers on final format
• Ensuring a fast path to a standard that meets the growing needs of EDA tool and IP Library providers
• Providing a foundation and structure for future collaboration and evolution of on-chip variation extensions

AvailabilityThe Liberty Technical Advisory Board is expected to finalize and ratify the OCV extensions to Liberty in November 2012, making it available to open-source licensees shortly thereafter.

• Learn more about Open Source Liberty at: http://www.opensourceliberty.org

About SynopsysSynopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys Achieves 100th Design Win with its 28-nm DesignWare® IP

Press release:

Synopsys Achieves 100th Design Win with its 28-nm DesignWare® IP

Tens of Millions of Units Shipped and More Than 30 Test Chip Tape-Outs Demonstrates DesignWare IP Robustness

MOUNTAIN VIEW, Calif., Sept. 5, 2012 /PRNewswire/ --
Highlights:

• Full line of  28-nm DesignWare IP includes PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries
• Availability spans four leading foundries and 10 unique processes, enabling designers to choose the IP that meets their specific design requirements
• Designed for SoC robustness with exhaustive simulations, reliability analysis and at-speed electrical characterization across process, voltage and temperature corners
• Optimized for a range of applications including mobile applications processors, multimedia graphics, networking and storage

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the 100th design win of its DesignWare IP optimized for 28-nanometer (nm) processes for multiple leading foundries. The silicon-proven 28-nm portfolio consists of widely-used IP including PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries, with tens of millions of units shipped.  Synopsys' 28-nm DesignWare IP has been thoroughly silicon-characterized across process, voltage and temperature (PVT) variations in both High-K Metal Gate and PolySiON technologies to ensure design robustness. By having taped out more than 30 test chips in more than ten different 28-nm process nodes, with products shipping in volume production, Synopsys provides designers with high-quality DesignWare IP solutions that can be quickly integrated into a range of system-on-chip (SoC) applications such as mobile applications processors, multimedia graphics networking and storage with less risk and effort.
"As an established IP provider, Synopsys has an extensive track record of delivering high-quality IP in leading process nodes," said Michael Chang, chairman of technical board at Global Unichip Corp. (GUC). "Our close collaboration with Synopsys through the years has enabled GUC to successfully incorporate a broad range of proven DesignWare IP in our customers' most advanced SoC designs. Synopsys' 28-nm IP will enable us to deliver next-generation designs for our customers with excellent margin and yield, while meeting power, performance and area requirements."
Advanced process geometries present additional design challenges in SoCs and IP development. At the 28-nm process node, design rules, leakage power and I/O voltages are substantially different than those in 40- and 65-nm processes. To address 28-nm design requirements, Synopsys modified key design aspects of its IP, while adhering to industry protocol specifications and ensuring reliable operation. For example, to meet manufacturing requirements, Synopsys implemented more than twice the number of restrictive design rule checks for its 28-nm IP compared to the 65-nm process and eight times the number of PVT corners for thorough validation. Furthermore, Synopsys employed advanced low-power design methodologies to address low leakage requirements.
Synopsys developed its 28-nm DesignWare embedded memories using statistical design methodologies to address design variability challenges and incorporated multiple power management features including source biasing and dual voltage rails to deliver up to 70 percent leakage power reduction. DesignWare Logic Libraries incorporate multiple threshold voltage and long channel devices to reduce SoC leakage power. In addition, the Logic Libraries are characterized across a wide range of corners, enabling designers to reduce dynamic power through the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques. These features and design techniques enable designers to successfully integrate 28-nm DesignWare IP into their advanced SoC designs to improve performance, power and area results.
"Developing 28-nm IP is not for the faint of heart. Synopsys has invested close to 100 staff-years in designing and verifying our 28-nm DesignWare IP to ensure interoperability and design robustness." said John Koeter, vice president of marketing for IP and systems at Synopsys. "Synopsys' user survey data indicates that approximately 50 percent of our customers' next designs will be implemented in 28-nanometer processes, so it is important that Synopsys provide designers with high-quality 28-nanometer IP in the timeframe they need to gain a competitive advantage."
AvailabilityThe DesignWare PHY IP for USB 3.0, USB 2.0, USB HSIC, DDR3/2, LPDDR3/2, PCIe 2.0, SATA I/II/III, HDMI 1.4, MIPI M-PHY, MIPI D-PHY, as well as embedded memories, logic libraries and data converters (analog-to-digital converters and digital-to-analog converters) for select 28-nm processes are available now.
The 28-nm DesignWare audio codecs are scheduled to be available to early adopters in Q4 of 2012.
About DesignWare IPSynopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware.
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

ARM and Synopsys Expand Collaboration to Optimize Power and Performance, and Accelerate Design and Verification for ARM Technology-based SoCs

Press release from Synopsys:

ARM and Synopsys Expand Collaboration to Optimize Power and Performance, and Accelerate Design and Verification for ARM Technology-based SoCs

CAMBRIDGE, United Kingdom and MOUNTAIN VIEW, Calif., Aug. 28, 2012 /PRNewswire/ --


Highlights:

• Industry leaders extend collaboration to benefit mutual customers across the broad ARM  partner ecosystem
• Synopsys licenses broad range of energy-efficient, high-performance ARM IP in multi-year agreement
• Collaboration to deliver power and performance optimized methodologies for ARM® Cortex™ processors using Synopsys' Galaxy™ Implementation Platform and ARM Artisan® physical IP and POP™ technology
• Synopsys' next-generation Discovery™ Verification IP (VIP) integrates new tests, checks and verification features to speed verification of AMBA® 4 ACE™-based System-on-Chips (SoCs)

ARM (LON: ARM; Nasdaq: ARMH) and Synopsys, Inc. (Nasdaq: SNPS) have signed a multi-year agreement that expands Synopsys' access to a broad range of ARM intellectual property (IP). The two companies will broaden their collaboration to enable SoC designers to optimize the power and performance of ARM technology-based SoCs with Synopsys Galaxy Implementation Platform and Discovery VIP, while reducing cost and decreasing time to market. Building on previous EDA tools and ARM Cortex-A15 processor license agreements, this new agreement provides Synopsys with access to a range of Cortex processors, including technology needed to implement ARM big.LITTLE™ processing, ARM Artisan physical IP, POP technology optimized for Cortex processor implementation, as well as CoreLink™ interconnect and AMBA 4 ACE system IP.

By expanding their collaboration to include the latest ARM technology, Synopsys will be able to create and deliver optimized tools and methodologies for the implementation and verification of ARM processing subsystems, and ARM will be able to enhance its IP. The ongoing partnership aims to meet demand from designers for SoCs that feature both extreme energy efficiency and high performance. For example, ARM big.LITTLE processing combines Cortex-A15 MPCore™ and Cortex-A7 MPCore processors with ARM CoreLink CCI-400 cache coherent interconnect to allow software to be migrated seamlessly to the optimum processor for each task. This paradigm enables up to 70 percent processor energy savings on common workloads.

"In today's increasingly competitive market environment, optimized solutions from two industry leaders can make a big difference for our partners designing ARM technology-based SoCs by accelerating the design process and driving gains in power and performance," said Simon Segars, executive vice president and general manager, Processor and Physical IP Divisions at ARM. "By providing Synopsys with wider access to industry-leading ARM IP, we are enabling mutual customers to benefit from streamlined design and verification, ultimately, decreasing time to market."

Combining ARM and Synopsys expertise, the optimized implementation flows will use Synopsys Galaxy tools and methodologies as well as ARM Artisan physical IP and POP solutions to better enable designers to produce Cortex-A9, Cortex-A15 and Cortex-A7 processor-based designs faster and with improved performance and power results. This solution is complemented by Synopsys' Virtualizer™ Design Kit (VDK) for ARM big.LITTLE processing, as well as by Synopsys' Discovery Verification IP and Protocol Analyzer for the AMBA 4 ACE specification.

In addition to using the ARM processor-optimized methodologies with Synopsys' Galaxy tools, designers can also use Synopsys' Lynx Design System for additional productivity and predictability through a tapeout-validated, SoC-level implementation flow. Synopsys provides optimized processor implementation training and design assistance to help customers achieve their target performance and power in their chosen semiconductor process technology. Synopsys will also optimize the Discovery Verification Platform for ARM IP. Discovery VIP and Protocol Analyzer integrate additional tests, system monitor checks and other features to accelerate verification of AMBA 4 ACE interconnect-based designs.
"Synopsys tools are used in a significant portion of leading-edge implementations of ARM processor-based SoCs, and our customers are pushing for extreme performance and power efficiency," said Deirdre Hanford, senior vice president, global technical services at Synopsys. "This expanded collaboration enables Synopsys and ARM to deliver the optimized solutions that SoC designers need to meet the power and performance requirements for their ARM-powered designs."

About ARM

ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM by following these links:

• ARM website: http://www.arm.com/
• ARM Connected Community: http://www.arm.com/community/
• ARM Blogs: http://blogs.arm.com/
• ARMFlix on YouTube: http://www.youtube.com/user/ARMflix
• ARM on Twitter:
  • http://twitter.com/ARMMobile
  • http://twitter.com/ARMCommunity
  • http://twitter.com/ARMEmbedded
  • http://twitter.com/ARMSoC
  • http://twitter.com/KeilTools
  • http://twitter.com/ARMMultimedia

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

ARM is a registered trademark of ARM Limited. Synopsys is a registered trademark of Synopsys, Inc. All other trademarks mentioned in this release are the intellectual property of their respective owners.

Synopsys Announces Results of Robert S. Hilbert Memorial Optical Design Competition

News release:

Synopsys Announces Results of Robert S. Hilbert Memorial Optical Design Competition

Annual Competition Recognizes Student Achievements in Optical Design

MOUNTAIN VIEW, Calif., Aug. 16, 2012 /PRNewswire/ -- Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, announced today that University of Rochester students Anthony Visconti and Brett Sternfield and University of Alabama in Huntsville student Josh Walters are the winners of the 2012 Robert S. Hilbert Memorial Optical Design Competition. The competition was established in 2000 by Optical Research Associates (ORA^®), now the Optical Solutions Group at Synopsys, and was named in honor of ORA's former president and chief executive officer Robert S. Hilbert. The annual competition is open to students in North America working toward a bachelor's, master's, or Ph.D. degree who utilize Synopsys' CODE V^® or LightTools^® software to perform optical design and engineering research. Awards are granted to students who have submitted papers that demonstrate optical design excellence.
Anthony Visconti of the University of Rochester was recognized for his work on infrared optical imaging using CODE V in his paper titled, "Optical Passive Athermalization Using Schott Chalcogenide Glasses." Applications of Visconti's project include thermal imaging for night vision systems, as well as remote sensing for aerial photography and satellite data collection. Brett Sternfield, also of the University of Rochester, was recognized for his work on a machine vision imaging system using CODE V in his paper titled, "190 Degree FFOV Fisheye for Autonomous Robots." Sternfield presents a method to improve a robot's ability to navigate a new environment and capture images, which can be useful for a wide range of tasks, including search and rescue missions, intelligence gathering and even fast food delivery.
Josh Walters of the University of Alabama in Huntsville was recognized for his project using CODE V titled, "Non-Sequential Modeling of Multi-Aperture Lenslet Array Spectropolarimetic Imager." The goal of Walters' design is to reduce crosstalk in an imaging system that uses an array of lenslets, so that the resulting image of each channel is clearly distinguished. This work will aid those researching the benefits of non-traditional imaging systems, similar to the compound eye found in insects.
"We believe it is important to encourage the next generation of optical engineers by recognizing and showcasing their talents in our annual student design competition," said George Bayz, vice president and general manager of the Optical Solutions Group at Synopsys. "The entries we received reflect strong design concepts that were well executed and presented and show promise for optical systems across a broad range of applications."
The three projects will be on display at SPIE Optics + Photonics (August 12-16, 2012, San Diego, Calif.) in Synopsys' booth 417.
About the Robert S. Hilbert Memorial Optical Design Competition
The annual Robert S. Hilbert Memorial Optical Design Competition recognizes excellence in optical design projects completed by students. The competition honors the memory of Robert Hilbert (1941-2008), former president and chief executive officer of Optical Research Associates, who was deeply committed throughout his career to fostering technical innovation in optics and supporting optics education. The competition is open to students enrolled in a post-secondary degree program in North America, working toward a bachelor's, master's or Ph.D. degree. To participate, students can enter an optical design class assignment or thesis work that uses CODE V or LightTools software. Awards totaling $4,000 are granted each year. For more information, visitwww.opticalres.com/student.
About Synopsys' Optical Solutions Group
Synopsys' Optical Solutions Group, formerly Optical Research Associates, is one of the world's leading developers of optical design and analysis tools, with CODE V imaging design software, LightTools illumination design software and RSoft products for photonic and optical network design. The group also provides optical systems design services, with more than 4,800 completed projects in imaging, illumination and optical systems engineering.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Synopsys Launches Industry's First Technical Community Site Dedicated to Users of Verification IP

Press release:

Synopsys Launches Industry's First Technical Community Site Dedicated to Users of Verification IP

VIP-Central.org Serves as an Online Resource Connecting Protocol and Verification IP Experts to SoC Verification Engineers

MOUNTAIN VIEW, Calif., Aug. 8, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the launch of VIP-Central.org, the first industry-wide, technical community site focused on system-on-chip (SoC) verification engineers and users of verification IP (VIP). The site provides a centralized online resource of relevant forums and blogs focused on verification of industry-standard protocols. VIP-Central.org is the go-to source for the latest technical information and discussions on the use of verification IP and advanced verification methodologies to verify protocol-based IP as well as IP integration, SoC sub-systems and full SoCs. VIP-Central.org aggregates information from industry experts across the verification community, providing best practices and ideas for better verification performance, protocol debug, methodology, verification planning, coverage management and ease-of-use.
"As each new SoC adds the next generations of different IP blocks, IP subsystems and frequent releases of new protocols, SoC companies are required to quickly ramp their verification teams to embrace these changes," said Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research. "The launch of VIP-Central.org as a technical resource for protocol-based verification will improve ramp times, act as a repository of knowledge and expertise for designers, and also enable the verification IP experts in the industry to share their best practices with the verification community."
With the increasing number of complex protocols used in SoCs, verification engineers face a tough challenge to quickly acquire the protocol expertise needed to verify a SoC as well as all of its on-chip fabrics and off-chip interfaces. The challenge is made tougher by the frequent release of new and more sophisticated generations of protocols to improve performance, power and quality of service. Verification engineers must complete many tasks requiring both protocol and methodology expertise including developing environments, integrating VIP, using and modifying test sequences, debugging complex protocol results and analyzing coverage data. VIP-Central.org is designed to help engineers quickly understand the intricacies and foibles of each protocol and how to effectively utilize industry-available verification IP to verify these protocols while employing methodologies such as UVM, OVM and VMM.
"VIP-Central.org represents an important milestone for the VIP user community," said Janick Bergeron, verification fellow at Synopsys. "As protocols become more intricate and SoC verification complexity continues to grow, VIP-Central.org offers a community-driven portal to share the learning from our successful customer VIP engagements, and enable exchange of ideas with other VIP experts, users and the entire SoC verification community."
About VIP-Central.org
VIP-Central.org is an industry-wide community site for system-on-chip (SoC) verification engineers and users of verification IP. It provides a centralized online resource of relevant forums and blogs focusing on verification of today's industry-standard protocols. Visit VIP-Central.org online at http://www.vip-central.org/.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Emulex to Continue Redesign of Products

Emulex to Continue Redesign of Products Impacting Five Percent of Net Revenues

Court Approves Continued Shipment of Impacted Products Worldwide

COSTA MESA, Calif., March 19, 2012 – Emulex Corporation (NYSE: ELX) today reported the continued implementation of design changes for products impacted by the issuance of an injunction for two patents by the U.S. District Court for the Central District of California in the lawsuit filed against Emulex by Broadcom Corporation (NASDAQ: BRCM), based on U.S. revenues for sales of impacted products that were about five percent of Emulex’s net revenues for its second quarter of fiscal 2012. The injunction included a “sunset period” of 18 months for Emulex to continue selling impacted products in the US without design changes. Based on the jury assessment of royalties, and the terms of the injunction, Emulex estimates a charge of approximately $600,000 in liability for damages to Broadcom to its third quarter fiscal 2012 GAAP results. This amount is in addition to the $387,922 in liability previously reported by Emulex for that patent during the first quarter of 2012.

For its second fiscal quarter which ended on January 1, 2012, Emulex reported net revenues of $128.7 million, 76 percent (or $97.8 million) of which came from outside the US based on billed-to location. For the second fiscal quarter of fiscal 2012, the net revenues in the US for products impacted by issuance of the injunction were approximately $7 million. The design changes primarily focus on serializer/deserializer (SerDes) modules, which Emulex does not design but obtains from several suppliers, and which are included in impacted Emulex products. The impacted Emulex products include BE2, BE3, XE201, SOC 320, SOC 422 and SOC 442 ASICs, and products containing those ASICs.

“Emulex is dedicated to protecting the interest of its customers,” said Jim McCluney, the Chief Executive Officer of Emulex. “We have been working with our suppliers to implement design changes to the SerDes modules included in the impacted products.”

Broadcom had earlier asserted 12 different US patents against Emulex. Emulex presented a vigorous defense prior to the trial, and only 6 patents remained by the time of trial. After three weeks of trial, the court determined that one of the patents (7,058,150) had been infringed by Emulex, and the jury rendered an advisory verdict to the Court that it is not invalid, and awarded $387,922 in damages with respect to that patent. Subsequently, the judge determined that a second patent (7,471,691) had been infringed by Emulex. With respect to the remaining four patents, the jury found one not infringed and could not reach a unanimous verdict on the other three. Emulex intends to continue to vigorously defend its products, including a potential appeal.

About Emulex

Emulex, the leader in converged networking solutions, provides enterprise-class connectivity for servers, networks and storage devices within the data center. The Company's product portfolio of Fibre Channel host bus adapters, network interface cards, converged network adapters, controllers, embedded bridges and switches, and connectivity management software are proven, tested and trusted by the world's largest and most demanding IT environments. Emulex solutions are used and offered by the industry's leading server and storage OEMs including, Cisco, Dell, EMC, Fujitsu, Hitachi, Hitachi Data Systems, HP, Huawei, IBM, NEC, NetApp and Oracle. Emulex is headquartered in Costa Mesa, Calif., and has offices and research facilities in North America, Asia and Europe. More information about Emulex (NYSE:ELX) is available at www.Emulex.com.

Press Release : March 06, 2012

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Veterans Affairs Selects HP to Improve Healthcare Claims Processing

Topics:Instant-On Enterprise

PALO ALTO, Calif. == HP today announced that the U.S. Department of Veterans Affairs (VA) has selected HP Enterprise Services to continue as a prime contractor for the Compensation and Pension Record Interchange (CAPRI) support program to help deliver quality healthcare to veterans.

HP will provide overall project management, business process analysis and testing services as well as software design, development and support services. The contract extends HP’s 10-year involvement with the CAPRI application, and the company’s relationship with the VA, which has spanned more than 12 years.

The CAPRI application enhances the efficiency of claims processing by allowing the Veterans Health Administration and the Veterans Benefits Administration to share medical data through the Bidirectional Health Information Exchange system. The CAPRI software provides online access to medical data, which enhances the timeliness of the benefits determination. This will facilitate expedited claims processing and improved quality of healthcare for disabled veterans.

“Providing quality healthcare in a timely manner to veterans is a top priority for the VA,” said Marilyn Crouther, senior vice president and general manager, U.S. Public Sector, HP Enterprise Services. “By enhancing the CAPRI application, HP and the VA will provide faster access to healthcare for veterans by expanding the VA’s information exchange network and expediting the claims cycle.”   

Over the term of the contract, HP will team with small, veteran-owned businesses Systems Made Simple Inc. and V-Tech Solutions Inc. to complete the project.

In support of the CAPRI Program, HP will deliver comprehensive, secure technology solutions to support the VA’s patient-centric delivery of high-quality healthcare to the country’s valued veterans.

In a world of continuous connectivity, HP enables agencies to become
Instant-On Governments with technology, security and innovation embedded throughout their organizations to deliver immediate services to citizens and clients. Clients will learn more at HP’s premier client event, HP Discover, which takes place June 4-7 in Las Vegas. 

More information about HP Enterprise Services’ government business is available atwww.hp.com/enterprise/government.

About HP

HP creates new possibilities for technology to have a meaningful impact on people, businesses, governments and society. The world’s largest technology company, HP brings together a portfolio that spans printing, personal computing, software, services and IT infrastructure to solve customer problems. More information about HP (NYSE: HPQ) is available at http://www.hp.com.

Energy Department Spurs Small Modular Nuclear Reactors

News release from the U.S. Dept. of Energy:

Energy Department Takes First Step to Spur U.S. Manufacturing of Small Modular Nuclear Reactors

January 20, 2012 

Washington, D.C. – The U.S. Department of Energy today announced the first step toward manufacturing small modular nuclear reactors (SMRs) in the United States, demonstrating the Administration’s commitment to advancing U.S. manufacturing leadership in low-carbon, next generation energy technologies and restarting the nation’s nuclear industry.  Through the draft Funding Opportunity Announcement announced today, the Department will establish cost-shared agreements with private industry to support the design and licensing of SMRs.

“America’s choice is clear - we can either develop the next generation of clean energy technologies, which will help create thousands of new jobs and export opportunities here in America, or we can wait for other countries to take the lead,” said Energy Secretary Steven Chu. “The funding opportunity announced today is a significant step forward in designing, manufacturing, and exporting U.S. small modular reactors, advancing our competitive edge in the global clean energy race.”

Small modular reactors, approximately one-third the size of current nuclear plants, have compact designs that are expected to offer a host of safety, siting, construction and economic benefits. Specifically, they could be made in factories and transported to sites where they would be ready to “plug and play” upon arrival, reducing both capital costs and construction times. The small size also makes SMRs ideal for small electric grids and for locations that cannot support large reactors, providing utilities with the flexibility to scale production as demand changes.

The draft Funding Opportunity Announcement (FOA) announced today solicits input from industry in advance of a full FOA, which will support first-of-a-kind engineering, design certification and licensing through a cost-shared partnership. The full FOA will fund up to two SMR designs with the goal of deploying these reactors by 2022.

Today’s announcement comes on the heels of the Nuclear Regulatory Commission’s certification of Westinghouse Electric’s AP1000 nuclear reactor design, which was supported through a cost-shared agreement with the Energy Department. The Department’s efforts, in coordination with the NRC and private industry, have helped American companies lead the way in obtaining certification and licensing approvals for new reactor designs, which will further streamline these processes for future investments in the U.S. nuclear industry.

For more information on SMRs, please visit the Office of Nuclear Energy website.