Synopsys Announces DesignWare DDR4 Memory Interface IP

News release:

Synopsys Announces DesignWare DDR4 Memory Interface IP

Memory Controller and PHY Support Multiple DDR Standards While Reducing Latency and Standby Power

MOUNTAIN VIEW, Calif., Sept. 18, 2012 /PRNewswire/ --
Highlights:

• Synopsys expands its industry-leading DesignWare® DDR Memory Interface IP family to include support for DDR4 SDRAMs
• Backward compatibility with DDR3 and LPDDR2/3 mobile SDRAMs gives SoC designers flexibility as they transition from one SDRAM standard to the next
• New DDR4 IP offers more features with up to 50 percent lower latency than the previous generation
• DDR4 memory controller and PHY are connected by a standard DFI 3.1 interface to streamline connections to custom PHYs and controllers

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the emerging DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.
"Synopsys' support for DDR4 memory is an important contribution to building a robust DDR4 ecosystem," said Robert Feurle, vice president of DRAM marketing for Micron Technology, Inc. "DDR4 brings substantial power and performance benefits to the industry, and Micron is aggressively driving its introduction. By implementing their DesignWare DDR Interface IP with backward compatibility in mind, Synopsys is enabling chip developers to bridge the transition from today's DDR3-based SoCs to the upcoming DDR4 designs."
Synopsys' DesignWare DDR4 IP solution consists of the DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface. The new DDR4 IP supports all key DDR4 features planned for the upcoming JEDEC standard and, compared to the previous version, includes a 13 percent increase in raw bandwidth, up to a 50 percent reduction in overall latency and new low-power features that provide intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns. Real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance and minimizing latency.
"While the initial target markets for DDR4 are networking, server, and compute platforms, engineers designing for digital TVs, set-top-boxes, multi-function printing, smartphone and tablet applications will also adopt DDR4 DRAM as prices drop and performance improves," said Desi Rhoden, executive vice president, Montage Technology, and JEDEC memory chairman. "Synopsys has leveraged their participation at JEDEC to develop DDR4-compatible products before the actual standard has been released, which is a key benefit of JEDEC membership."
"Synopsys' complete DDR interface IP portfolio includes support for LPDDR, LPDDR2, LPDDR3, DDR, DDR2, and DDR3," said John Koeter, vice president of marketing for IP and systems at Synopsys. "With this announcement, we are broadening our portfolio to include support for DDR4 while maintaining backward compatibility with existing JEDEC standard SDRAMs. As new DDR standards evolve, designers look for reliable solutions. Synopsys' track record of over 320 DDR IP design wins demonstrates that we offer a low-risk path to silicon success."
Availability
Availability for the DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4 is planned for Q4 2012.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for system-on-chip (SoC) designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer™ virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
Forward Looking Statements
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected availability of Synopsys' DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, unforeseen production or delivery delays, failure to perform as expected, product errors or defects and other risks detailed in Synopsys' filings with the U.S. Securities and Exchange Commission, including those described in the "Risk Factors" section of Synopsys' Quarterly Report on Form 10-Q for the fiscal quarter ended July 31, 2012.

Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance For 20nm and Below

Press release:

Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance For 20nm and Below

Advances Include Faster Runtime, ECO Flows and New Process Modeling Technology

MOUNTAIN VIEW, Calif., Sept. 6, 2012 /PRNewswire/ --
Highlights:

• Qualified by leading foundries for 20 nanometers (nm)
• Successful in numerous tapeouts targeted for 20nm
• Introduces new double patterning (DPT) decomposition checking and pattern matching technologies for optimal compliance with foundry manufacturing requirements 
• Enables reduced verification turnaround time with demonstrated scalability to 64 cores and beyond
• Expands In-Design technology for automatic DRC/DPT repair and 2X faster ECOs

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the release of IC Validator 2012.06, Synopsys' physical verification platform for advanced process nodes. With immediate availability of qualified rule decks by leading foundries, IC Validator 2012.06 offers new technologies that enable physical signoff verification at advanced process nodes. IC Validator 2012.06 continues to build on Synopsys' approach of speeding design closure through In-Design physical verification with Synopsys' IC Compiler^™ place and route solution, enabling place-and-route engineers to eliminate late stage surprises and manual repairs. New additions to the In-Design flow, targeted for 20nm and below, include DPT and pattern matching technology. This latest release of IC Validator also offers a significant performance boost for verifying large and complex 20-nm designs. By maximizing the utilization of mainstream computing hardware through innovative techniques, IC Validator can enable engineers to parallelize design rule checks (DRCs) on 64 processing cores and beyond, thereby significantly reducing verification turnaround time for these advanced process nodes.
"To address the complexities of 20nm process, we are actively expanding the use of In-Design Physical verification with IC Compiler and IC Validator for our new designs," said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics.
Enabling Physical Verification at 20nm and BelowTo address the stringent manufacturing requirements of 20-nm design, IC Validator 2012.06 introduces several new advances in process modeling technology:

• Double Patterning: The limitations of current lithographic technology require layout to be split into two masks of alternating structures. IC Validator features a fast and accurate, native decomposition ("coloring") engine. IC Validator can perform decomposition checks during design and can also drive automatic fixing of violations with IC Compiler via the In-Design technology. IC Validator can also perform the final signoff quality check alongside the final design rule check.
• Pattern Matching: Occasionally layout patterns can generate lithography hotspots, leading to accidental open or short connections. IC Validator's patented pattern-matching technology augments DRC with intuitive 2D multi-shape pattern analysis for ultra-fast detection of manufacturing hotspots. It can also drive automatic fixing of these hotspots with IC Compiler. Leading manufacturers will thus be able to achieve better process margins and higher yields for the 20-nm process node.

Improving Design Turnaround TimeIC Validator is being broadly used by design teams for In-Design physical verification with IC Compiler. This release complements IC Compiler 2012.06, allowing users to benefit from 2X faster ECO and automatic design repair (ADR) flows. New additions to In-Design technology also make it possible for designers to perform layout enhancement for yield natively within IC Compiler, streamlining the design flow and eliminating wasteful iterations.
In addition to being used for In-Design verification, IC Validator is also fully qualified for physical signoff at leading foundries across a broad range of process technologies. IC Validator 2012.06 deploys a range of distributed multiprocessing techniques to achieve optimal utilization of available hardware. These technologies, including multi-threading, on-demand load balancing and memory-aware scheduling, have demonstrated scalability to 64 cores and beyond. With this release, customers designing at advanced process nodes can now benefit from a significant productivity boost and faster turnaround times.
"IC Validator 2012.06 is the most noteworthy release for our physical verification product line to date," said Antun Domic, senior vice president and general manager of Synopsys' implementation group. "Beyond enabling verification of the highly complex 20-nanometer process technology node at Samsung and other leading foundries with a multitude of new technologies, we have added significant improvements in runtime, scalability and In-Design productivity that will benefit our entire customer base."
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Synopsys' RSoft OptSim Accelerates Design of Next-Generation Optical Communication Systems

Press release:

Synopsys' RSoft OptSim Accelerates Design of Next-Generation Optical Communication Systems

OptSim version 5.3 is now generally available

MOUNTAIN VIEW, Calif., Sept. 6, 2012 /PRNewswire/ --
Highlights:

• Expands support for modulation formats used in next-generation optical networks
• Accelerates design development with an expanded model library
• Speeds evaluation of optical signal propagation in data communication systems
• Increases user productivity with application examples

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the availability of the latest release of its RSoft™ Optical Communication Design Suite, which includes OptSim™ and its multimode companion tool ModeSYS™. OptSim version 5.3 delivers innovative modeling capabilities and new application examples that enable engineers to accelerate the design of high-performance optical communication systems.
"Optimized design of existing data links and the advancement of complex future designs can only be achieved with a thorough understanding of the underlying physics and technology involved, as well as the ability to predict performance and recognize design limitations," said Chris Kocot, principal scientist, Finisar Corporation. "At Finisar, simulation software is a crucial facilitator in this process. OptSim is a key component in our suite of software simulation tools used for advanced product development, including 28 Gb/s optical interconnects and next-generation optical links operating at 56 Gb/s per channel, as well as for high-speed link simulations that involve advanced modulation techniques."
Support for Cutting-Edge Modulation FormatsOptSim now includes models for accurately simulating coherent polarization-multiplexed binary phase-shift keying (PM-BPSK) as well as coherent multi-level polarization-multiplexed modulation formats such as PM-16QAM and PM-64QAM. These enhancements can help speed development of advanced applications such as single-carrier 100G Ethernet. The software also supports enhanced orthogonal frequency-division multiplexing (OFDM) models that can handle negative frequencies and calculate error vector magnitudes. This provides engineers with increased flexibility and power when developing OFDM-based systems, such as high-speed long-haul transmission systems with high inter-symbolic interference (ISI).
Application-Specific Models Accelerate Design DevelopmentOptSim now offers the following additions to its model library, which users can incorporate into their designs to jumpstart analysis of a wide range of systems, including photonic integrated circuits, long-reach and ultra-long-reach metro networks, and optical transport networks:

• Y-fed balanced-bridge dual-arm Mach-Zehnder modulator model
• Electrical filter synthesis based on data in Touchstone files
• Model of clipping in the electrical domain
• Phenomenological model for more easily implementing dispersion compensation

"OptSim has been a useful tool, giving us the ability to assess the performance of new systems before components are available for lab testing," said Steven Searcy, optical systems engineer, ADVA Optical Networking. "The ability to obtain preliminary design rules via simulation is critical to staying ahead in the development and introduction of new technologies."
Enhanced Multimode Fiber Modeling Speeds Evaluation of Optical Signal PropagationModeSYS includes an updated and enhanced multimode fiber model that provides faster calculation of mode-coupling equations. This can significantly accelerate evaluation of optical signal propagation in data communication systems.
Application Examples Increase User ProductivityNew application notes in OptSim demonstrate state-of-the-art examples that can reduce training time for new users and increase efficiency for experienced users. Application [examples] include polarization-multiplexed modulation formats, parametric fiber amplifiers, microwave photonics and multimode systems:

• PM-QPSK modulation using an external local oscillator
• Dual carrier PM-QPSK modulation
• In-band crosstalk in partial DPSK systems
• Phase-sensitive fiber parametric amplifiers
• Microwave photonic links based on balanced detection
• DMD test and measurement per IEC specification 60793-1-49
• EMB test and measurement per IEC specification 60793-1-41
• 25-Gbps directly modulated VCSEL-based multimode links

"OptSim 5.3 adds modeling enhancements that strengthen its standing as an ideal tool for optical communication design and simulation," said George Bayz, vice president and general manager of the Optical Solutions Group at Synopsys. "These new features are augmented by our continued focus on improving user productivity, with an expanded model library and detailed application notes. Our goal is to help engineers develop, test and deliver new systems more efficiently than ever."
Availability & ResourcesOptSim version 5.3 is available now and can be obtained by emailing rsoft_sales@synopsys.com. Learn more about Synopsys' RSoft products at http://www.synopsys.com/Tools/OpticalDesign.
About Synopsys' RSoft ProductsSynopsys' RSoft products are leading solutions in photonic design software and serve several industries including optical communications, optoelectronics and semiconductor manufacturing. RSoft products provide a full range of design, optimization and planning tools for optical communications, as well as solutions for optoelectronics components and subsystems.
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Synopsys' Open-Source Liberty Format to Incorporate On-Chip Variation Extensions

Press release:

Synopsys' Open-Source Liberty Format to Incorporate On-Chip Variation Extensions

Collaborating with Standards Board Industry Leaders to Ensure Broad Ecosystem Enablement

MOUNTAIN VIEW, Calif., Sept. 5, 2012 /PRNewswire/ --
Highlights:

• OCV extensions help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm
• Liberty Technical Advisory Board expected to finalize and ratify new extensions in November 2012

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced it intends to incorporate on-chip variation (OCV) extensions in its open-source Liberty™ library format, the de-facto modeling standard  for integrated circuit (IC) implementation and signoff. The new extensions will help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm processes nodes. The final format extensions and ratification as part of the Liberty standard will be completed with the guidance and assistance of the Liberty Technical Advisory Board.
The Liberty library format is the semiconductor industry's most widely adopted library standard used by virtually all EDA implementation, analysis and library characterization tools as the library model exchange for timing, noise, power and test behavior.  In May 2006, an industry-wide Liberty Technical Advisory Board was formed to facilitate the evolution of the Liberty library modeling standard. The Liberty Technical Advisory Board functions under the auspices of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). Its 14 member companies represent the broad semiconductor industry including the design community, EDA companies, silicon foundries, and semiconductor intellectual property (IP) companies. A complete list of members can be found at http://opensourceliberty.org/liberty_techadvisory.html. Liberty is available for download to the entire semiconductor design community under standard open-source terms. The latest Liberty syntax specifications and tools can be found at http://www.opensourceliberty.org.
"Standardizing the Liberty format extensions through the Liberty Technical Advisory Board allows the design community and EDA tool suppliers an opportunity to contribute and participate in the standardization process," said Rich Goldman, vice president of corporate marketing and strategic alliances, Synopsys. "In the past 2 years, the Liberty Technical Advisory Board has helped guide the ratification of over 10 new additions to Liberty to improve design for low-power flows."
The standardization of on-chip variation extensions via the Liberty Technical Advisory Board will benefit the semiconductor industry by:

• Allowing broad participation from the design community and EDA tool suppliers on final format
• Ensuring a fast path to a standard that meets the growing needs of EDA tool and IP Library providers
• Providing a foundation and structure for future collaboration and evolution of on-chip variation extensions

AvailabilityThe Liberty Technical Advisory Board is expected to finalize and ratify the OCV extensions to Liberty in November 2012, making it available to open-source licensees shortly thereafter.

• Learn more about Open Source Liberty at: http://www.opensourceliberty.org

About SynopsysSynopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys Achieves 100th Design Win with its 28-nm DesignWare® IP

Press release:

Synopsys Achieves 100th Design Win with its 28-nm DesignWare® IP

Tens of Millions of Units Shipped and More Than 30 Test Chip Tape-Outs Demonstrates DesignWare IP Robustness

MOUNTAIN VIEW, Calif., Sept. 5, 2012 /PRNewswire/ --
Highlights:

• Full line of  28-nm DesignWare IP includes PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries
• Availability spans four leading foundries and 10 unique processes, enabling designers to choose the IP that meets their specific design requirements
• Designed for SoC robustness with exhaustive simulations, reliability analysis and at-speed electrical characterization across process, voltage and temperature corners
• Optimized for a range of applications including mobile applications processors, multimedia graphics, networking and storage

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the 100th design win of its DesignWare IP optimized for 28-nanometer (nm) processes for multiple leading foundries. The silicon-proven 28-nm portfolio consists of widely-used IP including PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries, with tens of millions of units shipped.  Synopsys' 28-nm DesignWare IP has been thoroughly silicon-characterized across process, voltage and temperature (PVT) variations in both High-K Metal Gate and PolySiON technologies to ensure design robustness. By having taped out more than 30 test chips in more than ten different 28-nm process nodes, with products shipping in volume production, Synopsys provides designers with high-quality DesignWare IP solutions that can be quickly integrated into a range of system-on-chip (SoC) applications such as mobile applications processors, multimedia graphics networking and storage with less risk and effort.
"As an established IP provider, Synopsys has an extensive track record of delivering high-quality IP in leading process nodes," said Michael Chang, chairman of technical board at Global Unichip Corp. (GUC). "Our close collaboration with Synopsys through the years has enabled GUC to successfully incorporate a broad range of proven DesignWare IP in our customers' most advanced SoC designs. Synopsys' 28-nm IP will enable us to deliver next-generation designs for our customers with excellent margin and yield, while meeting power, performance and area requirements."
Advanced process geometries present additional design challenges in SoCs and IP development. At the 28-nm process node, design rules, leakage power and I/O voltages are substantially different than those in 40- and 65-nm processes. To address 28-nm design requirements, Synopsys modified key design aspects of its IP, while adhering to industry protocol specifications and ensuring reliable operation. For example, to meet manufacturing requirements, Synopsys implemented more than twice the number of restrictive design rule checks for its 28-nm IP compared to the 65-nm process and eight times the number of PVT corners for thorough validation. Furthermore, Synopsys employed advanced low-power design methodologies to address low leakage requirements.
Synopsys developed its 28-nm DesignWare embedded memories using statistical design methodologies to address design variability challenges and incorporated multiple power management features including source biasing and dual voltage rails to deliver up to 70 percent leakage power reduction. DesignWare Logic Libraries incorporate multiple threshold voltage and long channel devices to reduce SoC leakage power. In addition, the Logic Libraries are characterized across a wide range of corners, enabling designers to reduce dynamic power through the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques. These features and design techniques enable designers to successfully integrate 28-nm DesignWare IP into their advanced SoC designs to improve performance, power and area results.
"Developing 28-nm IP is not for the faint of heart. Synopsys has invested close to 100 staff-years in designing and verifying our 28-nm DesignWare IP to ensure interoperability and design robustness." said John Koeter, vice president of marketing for IP and systems at Synopsys. "Synopsys' user survey data indicates that approximately 50 percent of our customers' next designs will be implemented in 28-nanometer processes, so it is important that Synopsys provide designers with high-quality 28-nanometer IP in the timeframe they need to gain a competitive advantage."
AvailabilityThe DesignWare PHY IP for USB 3.0, USB 2.0, USB HSIC, DDR3/2, LPDDR3/2, PCIe 2.0, SATA I/II/III, HDMI 1.4, MIPI M-PHY, MIPI D-PHY, as well as embedded memories, logic libraries and data converters (analog-to-digital converters and digital-to-analog converters) for select 28-nm processes are available now.
The 28-nm DesignWare audio codecs are scheduled to be available to early adopters in Q4 of 2012.
About DesignWare IPSynopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware.
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

ARM and Synopsys Expand Collaboration to Optimize Power and Performance, and Accelerate Design and Verification for ARM Technology-based SoCs

Press release from Synopsys:

ARM and Synopsys Expand Collaboration to Optimize Power and Performance, and Accelerate Design and Verification for ARM Technology-based SoCs

CAMBRIDGE, United Kingdom and MOUNTAIN VIEW, Calif., Aug. 28, 2012 /PRNewswire/ --


Highlights:

• Industry leaders extend collaboration to benefit mutual customers across the broad ARM  partner ecosystem
• Synopsys licenses broad range of energy-efficient, high-performance ARM IP in multi-year agreement
• Collaboration to deliver power and performance optimized methodologies for ARM® Cortex™ processors using Synopsys' Galaxy™ Implementation Platform and ARM Artisan® physical IP and POP™ technology
• Synopsys' next-generation Discovery™ Verification IP (VIP) integrates new tests, checks and verification features to speed verification of AMBA® 4 ACE™-based System-on-Chips (SoCs)

ARM (LON: ARM; Nasdaq: ARMH) and Synopsys, Inc. (Nasdaq: SNPS) have signed a multi-year agreement that expands Synopsys' access to a broad range of ARM intellectual property (IP). The two companies will broaden their collaboration to enable SoC designers to optimize the power and performance of ARM technology-based SoCs with Synopsys Galaxy Implementation Platform and Discovery VIP, while reducing cost and decreasing time to market. Building on previous EDA tools and ARM Cortex-A15 processor license agreements, this new agreement provides Synopsys with access to a range of Cortex processors, including technology needed to implement ARM big.LITTLE™ processing, ARM Artisan physical IP, POP technology optimized for Cortex processor implementation, as well as CoreLink™ interconnect and AMBA 4 ACE system IP.

By expanding their collaboration to include the latest ARM technology, Synopsys will be able to create and deliver optimized tools and methodologies for the implementation and verification of ARM processing subsystems, and ARM will be able to enhance its IP. The ongoing partnership aims to meet demand from designers for SoCs that feature both extreme energy efficiency and high performance. For example, ARM big.LITTLE processing combines Cortex-A15 MPCore™ and Cortex-A7 MPCore processors with ARM CoreLink CCI-400 cache coherent interconnect to allow software to be migrated seamlessly to the optimum processor for each task. This paradigm enables up to 70 percent processor energy savings on common workloads.

"In today's increasingly competitive market environment, optimized solutions from two industry leaders can make a big difference for our partners designing ARM technology-based SoCs by accelerating the design process and driving gains in power and performance," said Simon Segars, executive vice president and general manager, Processor and Physical IP Divisions at ARM. "By providing Synopsys with wider access to industry-leading ARM IP, we are enabling mutual customers to benefit from streamlined design and verification, ultimately, decreasing time to market."

Combining ARM and Synopsys expertise, the optimized implementation flows will use Synopsys Galaxy tools and methodologies as well as ARM Artisan physical IP and POP solutions to better enable designers to produce Cortex-A9, Cortex-A15 and Cortex-A7 processor-based designs faster and with improved performance and power results. This solution is complemented by Synopsys' Virtualizer™ Design Kit (VDK) for ARM big.LITTLE processing, as well as by Synopsys' Discovery Verification IP and Protocol Analyzer for the AMBA 4 ACE specification.

In addition to using the ARM processor-optimized methodologies with Synopsys' Galaxy tools, designers can also use Synopsys' Lynx Design System for additional productivity and predictability through a tapeout-validated, SoC-level implementation flow. Synopsys provides optimized processor implementation training and design assistance to help customers achieve their target performance and power in their chosen semiconductor process technology. Synopsys will also optimize the Discovery Verification Platform for ARM IP. Discovery VIP and Protocol Analyzer integrate additional tests, system monitor checks and other features to accelerate verification of AMBA 4 ACE interconnect-based designs.
"Synopsys tools are used in a significant portion of leading-edge implementations of ARM processor-based SoCs, and our customers are pushing for extreme performance and power efficiency," said Deirdre Hanford, senior vice president, global technical services at Synopsys. "This expanded collaboration enables Synopsys and ARM to deliver the optimized solutions that SoC designers need to meet the power and performance requirements for their ARM-powered designs."

About ARM

ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM by following these links:

• ARM website: http://www.arm.com/
• ARM Connected Community: http://www.arm.com/community/
• ARM Blogs: http://blogs.arm.com/
• ARMFlix on YouTube: http://www.youtube.com/user/ARMflix
• ARM on Twitter:
  • http://twitter.com/ARMMobile
  • http://twitter.com/ARMCommunity
  • http://twitter.com/ARMEmbedded
  • http://twitter.com/ARMSoC
  • http://twitter.com/KeilTools
  • http://twitter.com/ARMMultimedia

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

ARM is a registered trademark of ARM Limited. Synopsys is a registered trademark of Synopsys, Inc. All other trademarks mentioned in this release are the intellectual property of their respective owners.

Synopsys Posts Financial Results for Third Quarter Fiscal Year 2012

For news release, click the link below:

http://synopsys.mediaroom.com/index.php?s=43&item=1057

Synopsys Announces Results of Robert S. Hilbert Memorial Optical Design Competition

News release:

Synopsys Announces Results of Robert S. Hilbert Memorial Optical Design Competition

Annual Competition Recognizes Student Achievements in Optical Design

MOUNTAIN VIEW, Calif., Aug. 16, 2012 /PRNewswire/ -- Synopsys, Inc., a world leader in software and IP for semiconductor design, verification and manufacturing, announced today that University of Rochester students Anthony Visconti and Brett Sternfield and University of Alabama in Huntsville student Josh Walters are the winners of the 2012 Robert S. Hilbert Memorial Optical Design Competition. The competition was established in 2000 by Optical Research Associates (ORA^®), now the Optical Solutions Group at Synopsys, and was named in honor of ORA's former president and chief executive officer Robert S. Hilbert. The annual competition is open to students in North America working toward a bachelor's, master's, or Ph.D. degree who utilize Synopsys' CODE V^® or LightTools^® software to perform optical design and engineering research. Awards are granted to students who have submitted papers that demonstrate optical design excellence.
Anthony Visconti of the University of Rochester was recognized for his work on infrared optical imaging using CODE V in his paper titled, "Optical Passive Athermalization Using Schott Chalcogenide Glasses." Applications of Visconti's project include thermal imaging for night vision systems, as well as remote sensing for aerial photography and satellite data collection. Brett Sternfield, also of the University of Rochester, was recognized for his work on a machine vision imaging system using CODE V in his paper titled, "190 Degree FFOV Fisheye for Autonomous Robots." Sternfield presents a method to improve a robot's ability to navigate a new environment and capture images, which can be useful for a wide range of tasks, including search and rescue missions, intelligence gathering and even fast food delivery.
Josh Walters of the University of Alabama in Huntsville was recognized for his project using CODE V titled, "Non-Sequential Modeling of Multi-Aperture Lenslet Array Spectropolarimetic Imager." The goal of Walters' design is to reduce crosstalk in an imaging system that uses an array of lenslets, so that the resulting image of each channel is clearly distinguished. This work will aid those researching the benefits of non-traditional imaging systems, similar to the compound eye found in insects.
"We believe it is important to encourage the next generation of optical engineers by recognizing and showcasing their talents in our annual student design competition," said George Bayz, vice president and general manager of the Optical Solutions Group at Synopsys. "The entries we received reflect strong design concepts that were well executed and presented and show promise for optical systems across a broad range of applications."
The three projects will be on display at SPIE Optics + Photonics (August 12-16, 2012, San Diego, Calif.) in Synopsys' booth 417.
About the Robert S. Hilbert Memorial Optical Design Competition
The annual Robert S. Hilbert Memorial Optical Design Competition recognizes excellence in optical design projects completed by students. The competition honors the memory of Robert Hilbert (1941-2008), former president and chief executive officer of Optical Research Associates, who was deeply committed throughout his career to fostering technical innovation in optics and supporting optics education. The competition is open to students enrolled in a post-secondary degree program in North America, working toward a bachelor's, master's or Ph.D. degree. To participate, students can enter an optical design class assignment or thesis work that uses CODE V or LightTools software. Awards totaling $4,000 are granted each year. For more information, visitwww.opticalres.com/student.
About Synopsys' Optical Solutions Group
Synopsys' Optical Solutions Group, formerly Optical Research Associates, is one of the world's leading developers of optical design and analysis tools, with CODE V imaging design software, LightTools illumination design software and RSoft products for photonic and optical network design. The group also provides optical systems design services, with more than 4,800 completed projects in imaging, illumination and optical systems engineering.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Seventh Annual International Microelectronics Olympiad of Armenia to be Hosted by Synopsys in Cooperation with IEEE TTTC

Press release:

Seventh Annual International Microelectronics Olympiad of Armenia to be Hosted by Synopsys in Cooperation with IEEE TTTC

Participation by the world's largest professional engineering association highlights the Olympiad's growing international reputation

YEREVAN, Armenia, Aug. 9, 2012 /PRNewswire/ -- Synopsys, Inc., a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that the Seventh Annual International Microelectronics Olympiad of Armenia will be held on October 4, 2012 in Yerevan, Armenia. For the first time, the event will be held in cooperation with the Institute of Electrical and Electronics Engineers (IEEE) Test Technology Technical Council (TTTC). IEEE's participation highlights the contest's growing international reputation.
Initiated in 2006, the Olympiad is held under the patronage of the Prime Minister of Armenia. Synopsys Armenia CJSC is the general organizer and a sponsor of the Olympiad. The general sponsor is Vivacell-MTS, Armenia's leading mobile operator. The Olympiad is also sponsored by Unicomp CJSC, Enterprise Incubator Foundation, Microsoft RA, Union of Manufacturers and Businessmen of Armenia, Union of Information Technology Enterprises, Arminco CJSC, Viasphere Technopark and INGO ARMENIA ICJSC.
In keeping with the theme of "Meeting the Challenges of Design and Test," the contestants in the Olympiad will compete in the areas of digital IC design and test, analog and mixed-signal IC design and test, semiconductor devices and technology, and mathematic and algorithmic issues of electronic design automation (EDA).
Guided by the motto "Recognize the best, inspire the next," the Olympiad aims to highlight the brightest, most talented engineers under the age of 30. The Olympiad goals are to stimulate further development of microelectronics in Armenia and in the participating countries by: recognizing and inspiring talented engineers; increasing interest in microelectronics among young specialists; discerning the level of knowledge of participants in the field of microelectronics in order to make necessary adjustments to regional educational programs; and creating a community of young specialists involved in microelectronics.
"The first Armenian Microelectronics Olympiad in 2006 attracted 82 participants. The event has since grown to an international contest including numerous award categories and 349 participants from 12 countries," said Rich Goldman, the president of the Olympiad Organizing Committee, CEO of Synopsys Armenia and vice president for Corporate Marketing and Strategic Alliances at Synopsys. "Working with IEEE will enable further growth. As one of the world's most respected and recognized professional engineering societies, the IEEE sponsors more than 1000 annual conferences and meetings in 81 countries and is highly involved in the technical program development of numerous events including trade shows, training workshops, and job fairs. IEEE's recognition of the Olympiad also benefits Armenia by highlighting it as a Center of Excellence for Microelectronics Education."
"This collaboration is a win-win-win situation for IEEE, for the Olympiad, and for Armenia as a country," said Dr. Yervant Zorian, president of the IEEE TTTC and chief architect at Synopsys. "The involvement of IEEE, the largest organization of electrical and electronic engineers, helps the Olympiad gain more international recognition. The Olympiad contributes to IEEE's efforts to encourage and support an interest in technology in young adults; holding the contest in Armenia highlights the country's technical leadership."
"The IEEE TTTC's decision to endorse the Annual International Microelectronics Olympiad is a key acknowledgement of its success in promoting technology development in this region over the past six years," said Vazgen Melikyan, president of the Olympiad Program Committee, director of Synopsys Armenia Educational Department (SAED), honorable scientist of Armenia and Sc.D. professor. "I am confident the cooperation of IEEE TTTC will result in a significantly greater number of highly knowledgeable participants from around the globe."
About IEEE TTTCIEEE is the world's largest professional association dedicated to advancing technological innovation and excellence for the benefit of humanity. Sponsored by IEEE's Computer Society, TTTC is a dedicated council to serve the global test technology professional community through a series of annual conferences, standards, publications, educational and professional activities. For more information, please visit http://tab.computer.org/tttc
About Synopsys Armenia CJSC and Synopsys, Inc. Synopsys, Inc. is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP), prototyping and services used in semiconductor design, verification and manufacturing. Synopsys established a presence in Armenia in 2004 as Synopsys Armenia closed joint stock company (CJSC). Synopsys Armenia CJSC provides R&D and product support in EDA, design for manufacturing (DFM) and the development of semiconductor intellectual property (IP). Employing several hundred qualified Armenian engineers, Synopsys is one of largest IT employers in Armenia. To encourage the highest levels of accomplishment for students in IT, the company sponsors awards and competitions such as theAnnual Educational Awards of the Republic of Armenia (RA) President, and the Annual International Microelectronics Olympiad of Armenia. Synopsys Armenia's investment in the community reaches well beyond IT. In 2010, Synopsys in Armenia was recognized as one of 12 finalists for the U.S. Secretary of State's annual Award for Corporate Excellence (ACE), citing the company's technology and financial leadership as well as its charity work and volunteer activities. Synopsys Armenia CJSC is located in Yerevan. Synopsys, Inc. is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys, Inc. and Synopsys Armenia online at http://www.synopsys.com andhttp://www.synopsys.am.

Synopsys Unveils Virtualizer Development Kits to Accelerate Software Development for ARM big.LITTLE Processing

Synopsys Unveils Virtualizer Development Kits to Accelerate Software Development for ARM big.LITTLE Processing

VDK Family Delivers Fast Software Bring-Up and Better Debug Control for Quad-Core ARM® Cortex™-A15 MPCore™ Processor and ARM big.LITTLE™ Processing-Based Designs

Mar 21, 2012

Highlights:

• VDKs are software development tools integrating fast, functional models of specific multicore systems, multicore software debugging/analysis tools and reference software stacks
• Software development up to 12 months before board availability
• Out-of-the-box support for Linux, Android and multicore task migration software to speed software development for ARM big.LITTLE processing
• Plug-n-play integration with software debuggers from ARM, Lauterbach and GNU
• Multicore/multicluster software analysis capabilities to best utilize big.LITTLE processing performance and energy efficiency capabilities
• Configurable Cortex processor subsystem, customizable by adding other system components

MOUNTAIN VIEW, Calif., March 21, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the first release of the Virtualizer™ Development Kit (VDK) Family for accelerating software development. The VDK Family for ARM Cortex Processors contains multiple reference designs, analysis and debug software tools for the Cortex-A15 MPCore processor and ARM big.LITTLE processing. By using the VDKs developers can now optimize for performance and energy efficiency prior to board availability. The reference designs can easily be customized for device specific requirements using Synopsys' Virtualizer solution.
"Synopsys' virtual prototyping technology has helped us accelerate software development before with great results, as we were able to demonstrate with the OMAP5430 processor," said Vincent Verfaillie, development platforms and tools manager, Texas Instruments Incorporated (TI). "We continue to use their VDK solution to deliver the capabilities we need for early software development and a fast ramp up with our big.LITTLE processing platform."
Increased Software Control and Visibility
The visibility and controllability offered by the Synopsys VDK for big.LITTLE processing-based designs enable debug and analysis capabilities that allow software developers to optimize big.LITTLE processing-based designs for performance and energy-efficiency. Using Synopsys' VDK, developers for innovative mobile and consumer devices can optimize their code based on realistic end user experiences as well as minimize software/hardware integration issues. The VDK offers developers the ability to optimize Linux, Android and big.LITTLE power management using record and replay of real world scenarios.
"As companies are adopting our big.LITTLE processing to enable both next generation performance and energy-efficiency for smart, connected devices, ARM and its partners have paved the way by encouraging a strong ecosystem," said Jim Nicholas, vice president of marketing, processor division, ARM. "By offering the VDK Family for ARM Cortex Processors, supporting our Cortex-A15 MPCore and big.LITTLE processing, Synopsys is able to offer this partner ecosystem a highly effective solution for early software development and help facilitate innovation."

Pre-configured for Android, Linux and big.LITTLE Processing
The VDK Family for ARM Cortex Processors comes pre-configured for Linux (Vanilla 2.6.38) and Android (Gingerbread 2.3.4) operating systems (OS) as a starting point for developing actual device software. In addition, the VDK Family is pre-configured for the multicore task migration software layer between the big.LITTLE processing cluster, which includes ARM Cortex-A15 MPCore and Cortex-A7 MPCore processors, and the client OS. This layer dynamically migrates the software between the processors for performance and power optimization. The VDK allows developers to take advantage of this new layer and provides support for debugging and optimizing the software running on multicore hardware like big.LITTLE processing. These VDKs include common interfaces and peripherals such as: USB3.0, Ethernet, UART, LCD, keyboard, battery, memory, and more.
 "Synopsys' first VDK family empowers customers like Texas Instruments to take full advantage of ARM's latest processing technology and reduce time-to-market for their next- generation products," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Synopsys' VDKs targeted for big.LITTLE processing and Cortex-A15 processor-based designs provide software developers with the necessary tools to optimize software much earlier in their project development cycle."
Availability
The VDK Family for ARM Cortex Processors will be generally available in the second quarter of calendar year 2012.
For more information about Synopsys' Virtualizer Development Kit Family, including compatibility with ARM tools and popular software debuggers, please visit: www.synopsys.com/VDK4big-LITTLE.