Synopsys Announces DesignWare DDR4 Memory Interface IP

News release:

Synopsys Announces DesignWare DDR4 Memory Interface IP

Memory Controller and PHY Support Multiple DDR Standards While Reducing Latency and Standby Power

MOUNTAIN VIEW, Calif., Sept. 18, 2012 /PRNewswire/ --
Highlights:

• Synopsys expands its industry-leading DesignWare® DDR Memory Interface IP family to include support for DDR4 SDRAMs
• Backward compatibility with DDR3 and LPDDR2/3 mobile SDRAMs gives SoC designers flexibility as they transition from one SDRAM standard to the next
• New DDR4 IP offers more features with up to 50 percent lower latency than the previous generation
• DDR4 memory controller and PHY are connected by a standard DFI 3.1 interface to streamline connections to custom PHYs and controllers

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the emerging DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.
"Synopsys' support for DDR4 memory is an important contribution to building a robust DDR4 ecosystem," said Robert Feurle, vice president of DRAM marketing for Micron Technology, Inc. "DDR4 brings substantial power and performance benefits to the industry, and Micron is aggressively driving its introduction. By implementing their DesignWare DDR Interface IP with backward compatibility in mind, Synopsys is enabling chip developers to bridge the transition from today's DDR3-based SoCs to the upcoming DDR4 designs."
Synopsys' DesignWare DDR4 IP solution consists of the DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface. The new DDR4 IP supports all key DDR4 features planned for the upcoming JEDEC standard and, compared to the previous version, includes a 13 percent increase in raw bandwidth, up to a 50 percent reduction in overall latency and new low-power features that provide intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns. Real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance and minimizing latency.
"While the initial target markets for DDR4 are networking, server, and compute platforms, engineers designing for digital TVs, set-top-boxes, multi-function printing, smartphone and tablet applications will also adopt DDR4 DRAM as prices drop and performance improves," said Desi Rhoden, executive vice president, Montage Technology, and JEDEC memory chairman. "Synopsys has leveraged their participation at JEDEC to develop DDR4-compatible products before the actual standard has been released, which is a key benefit of JEDEC membership."
"Synopsys' complete DDR interface IP portfolio includes support for LPDDR, LPDDR2, LPDDR3, DDR, DDR2, and DDR3," said John Koeter, vice president of marketing for IP and systems at Synopsys. "With this announcement, we are broadening our portfolio to include support for DDR4 while maintaining backward compatibility with existing JEDEC standard SDRAMs. As new DDR standards evolve, designers look for reliable solutions. Synopsys' track record of over 320 DDR IP design wins demonstrates that we offer a low-risk path to silicon success."
Availability
Availability for the DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4 is planned for Q4 2012.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for system-on-chip (SoC) designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer™ virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
Forward Looking Statements
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected availability of Synopsys' DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, unforeseen production or delivery delays, failure to perform as expected, product errors or defects and other risks detailed in Synopsys' filings with the U.S. Securities and Exchange Commission, including those described in the "Risk Factors" section of Synopsys' Quarterly Report on Form 10-Q for the fiscal quarter ended July 31, 2012.

Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance For 20nm and Below

Press release:

Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance For 20nm and Below

Advances Include Faster Runtime, ECO Flows and New Process Modeling Technology

MOUNTAIN VIEW, Calif., Sept. 6, 2012 /PRNewswire/ --
Highlights:

• Qualified by leading foundries for 20 nanometers (nm)
• Successful in numerous tapeouts targeted for 20nm
• Introduces new double patterning (DPT) decomposition checking and pattern matching technologies for optimal compliance with foundry manufacturing requirements 
• Enables reduced verification turnaround time with demonstrated scalability to 64 cores and beyond
• Expands In-Design technology for automatic DRC/DPT repair and 2X faster ECOs

Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the release of IC Validator 2012.06, Synopsys' physical verification platform for advanced process nodes. With immediate availability of qualified rule decks by leading foundries, IC Validator 2012.06 offers new technologies that enable physical signoff verification at advanced process nodes. IC Validator 2012.06 continues to build on Synopsys' approach of speeding design closure through In-Design physical verification with Synopsys' IC Compiler^™ place and route solution, enabling place-and-route engineers to eliminate late stage surprises and manual repairs. New additions to the In-Design flow, targeted for 20nm and below, include DPT and pattern matching technology. This latest release of IC Validator also offers a significant performance boost for verifying large and complex 20-nm designs. By maximizing the utilization of mainstream computing hardware through innovative techniques, IC Validator can enable engineers to parallelize design rule checks (DRCs) on 64 processing cores and beyond, thereby significantly reducing verification turnaround time for these advanced process nodes.
"To address the complexities of 20nm process, we are actively expanding the use of In-Design Physical verification with IC Compiler and IC Validator for our new designs," said Kyu-Myung Choi, senior vice president of Infrastructure Design Center, Samsung Electronics.
Enabling Physical Verification at 20nm and BelowTo address the stringent manufacturing requirements of 20-nm design, IC Validator 2012.06 introduces several new advances in process modeling technology:

• Double Patterning: The limitations of current lithographic technology require layout to be split into two masks of alternating structures. IC Validator features a fast and accurate, native decomposition ("coloring") engine. IC Validator can perform decomposition checks during design and can also drive automatic fixing of violations with IC Compiler via the In-Design technology. IC Validator can also perform the final signoff quality check alongside the final design rule check.
• Pattern Matching: Occasionally layout patterns can generate lithography hotspots, leading to accidental open or short connections. IC Validator's patented pattern-matching technology augments DRC with intuitive 2D multi-shape pattern analysis for ultra-fast detection of manufacturing hotspots. It can also drive automatic fixing of these hotspots with IC Compiler. Leading manufacturers will thus be able to achieve better process margins and higher yields for the 20-nm process node.

Improving Design Turnaround TimeIC Validator is being broadly used by design teams for In-Design physical verification with IC Compiler. This release complements IC Compiler 2012.06, allowing users to benefit from 2X faster ECO and automatic design repair (ADR) flows. New additions to In-Design technology also make it possible for designers to perform layout enhancement for yield natively within IC Compiler, streamlining the design flow and eliminating wasteful iterations.
In addition to being used for In-Design verification, IC Validator is also fully qualified for physical signoff at leading foundries across a broad range of process technologies. IC Validator 2012.06 deploys a range of distributed multiprocessing techniques to achieve optimal utilization of available hardware. These technologies, including multi-threading, on-demand load balancing and memory-aware scheduling, have demonstrated scalability to 64 cores and beyond. With this release, customers designing at advanced process nodes can now benefit from a significant productivity boost and faster turnaround times.
"IC Validator 2012.06 is the most noteworthy release for our physical verification product line to date," said Antun Domic, senior vice president and general manager of Synopsys' implementation group. "Beyond enabling verification of the highly complex 20-nanometer process technology node at Samsung and other leading foundries with a multitude of new technologies, we have added significant improvements in runtime, scalability and In-Design productivity that will benefit our entire customer base."
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

Synopsys' Open-Source Liberty Format to Incorporate On-Chip Variation Extensions

Press release:

Synopsys' Open-Source Liberty Format to Incorporate On-Chip Variation Extensions

Collaborating with Standards Board Industry Leaders to Ensure Broad Ecosystem Enablement

MOUNTAIN VIEW, Calif., Sept. 5, 2012 /PRNewswire/ --
Highlights:

• OCV extensions help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm
• Liberty Technical Advisory Board expected to finalize and ratify new extensions in November 2012

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced it intends to incorporate on-chip variation (OCV) extensions in its open-source Liberty™ library format, the de-facto modeling standard  for integrated circuit (IC) implementation and signoff. The new extensions will help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm processes nodes. The final format extensions and ratification as part of the Liberty standard will be completed with the guidance and assistance of the Liberty Technical Advisory Board.
The Liberty library format is the semiconductor industry's most widely adopted library standard used by virtually all EDA implementation, analysis and library characterization tools as the library model exchange for timing, noise, power and test behavior.  In May 2006, an industry-wide Liberty Technical Advisory Board was formed to facilitate the evolution of the Liberty library modeling standard. The Liberty Technical Advisory Board functions under the auspices of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). Its 14 member companies represent the broad semiconductor industry including the design community, EDA companies, silicon foundries, and semiconductor intellectual property (IP) companies. A complete list of members can be found at http://opensourceliberty.org/liberty_techadvisory.html. Liberty is available for download to the entire semiconductor design community under standard open-source terms. The latest Liberty syntax specifications and tools can be found at http://www.opensourceliberty.org.
"Standardizing the Liberty format extensions through the Liberty Technical Advisory Board allows the design community and EDA tool suppliers an opportunity to contribute and participate in the standardization process," said Rich Goldman, vice president of corporate marketing and strategic alliances, Synopsys. "In the past 2 years, the Liberty Technical Advisory Board has helped guide the ratification of over 10 new additions to Liberty to improve design for low-power flows."
The standardization of on-chip variation extensions via the Liberty Technical Advisory Board will benefit the semiconductor industry by:

• Allowing broad participation from the design community and EDA tool suppliers on final format
• Ensuring a fast path to a standard that meets the growing needs of EDA tool and IP Library providers
• Providing a foundation and structure for future collaboration and evolution of on-chip variation extensions

AvailabilityThe Liberty Technical Advisory Board is expected to finalize and ratify the OCV extensions to Liberty in November 2012, making it available to open-source licensees shortly thereafter.

• Learn more about Open Source Liberty at: http://www.opensourceliberty.org

About SynopsysSynopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys Achieves 100th Design Win with its 28-nm DesignWare® IP

Press release:

Synopsys Achieves 100th Design Win with its 28-nm DesignWare® IP

Tens of Millions of Units Shipped and More Than 30 Test Chip Tape-Outs Demonstrates DesignWare IP Robustness

MOUNTAIN VIEW, Calif., Sept. 5, 2012 /PRNewswire/ --
Highlights:

• Full line of  28-nm DesignWare IP includes PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries
• Availability spans four leading foundries and 10 unique processes, enabling designers to choose the IP that meets their specific design requirements
• Designed for SoC robustness with exhaustive simulations, reliability analysis and at-speed electrical characterization across process, voltage and temperature corners
• Optimized for a range of applications including mobile applications processors, multimedia graphics, networking and storage

Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the 100th design win of its DesignWare IP optimized for 28-nanometer (nm) processes for multiple leading foundries. The silicon-proven 28-nm portfolio consists of widely-used IP including PHYs for USB, PCI Express, SATA, HDMI, DDR, MIPI, as well as data converters, audio codecs, embedded memories and logic libraries, with tens of millions of units shipped.  Synopsys' 28-nm DesignWare IP has been thoroughly silicon-characterized across process, voltage and temperature (PVT) variations in both High-K Metal Gate and PolySiON technologies to ensure design robustness. By having taped out more than 30 test chips in more than ten different 28-nm process nodes, with products shipping in volume production, Synopsys provides designers with high-quality DesignWare IP solutions that can be quickly integrated into a range of system-on-chip (SoC) applications such as mobile applications processors, multimedia graphics networking and storage with less risk and effort.
"As an established IP provider, Synopsys has an extensive track record of delivering high-quality IP in leading process nodes," said Michael Chang, chairman of technical board at Global Unichip Corp. (GUC). "Our close collaboration with Synopsys through the years has enabled GUC to successfully incorporate a broad range of proven DesignWare IP in our customers' most advanced SoC designs. Synopsys' 28-nm IP will enable us to deliver next-generation designs for our customers with excellent margin and yield, while meeting power, performance and area requirements."
Advanced process geometries present additional design challenges in SoCs and IP development. At the 28-nm process node, design rules, leakage power and I/O voltages are substantially different than those in 40- and 65-nm processes. To address 28-nm design requirements, Synopsys modified key design aspects of its IP, while adhering to industry protocol specifications and ensuring reliable operation. For example, to meet manufacturing requirements, Synopsys implemented more than twice the number of restrictive design rule checks for its 28-nm IP compared to the 65-nm process and eight times the number of PVT corners for thorough validation. Furthermore, Synopsys employed advanced low-power design methodologies to address low leakage requirements.
Synopsys developed its 28-nm DesignWare embedded memories using statistical design methodologies to address design variability challenges and incorporated multiple power management features including source biasing and dual voltage rails to deliver up to 70 percent leakage power reduction. DesignWare Logic Libraries incorporate multiple threshold voltage and long channel devices to reduce SoC leakage power. In addition, the Logic Libraries are characterized across a wide range of corners, enabling designers to reduce dynamic power through the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques. These features and design techniques enable designers to successfully integrate 28-nm DesignWare IP into their advanced SoC designs to improve performance, power and area results.
"Developing 28-nm IP is not for the faint of heart. Synopsys has invested close to 100 staff-years in designing and verifying our 28-nm DesignWare IP to ensure interoperability and design robustness." said John Koeter, vice president of marketing for IP and systems at Synopsys. "Synopsys' user survey data indicates that approximately 50 percent of our customers' next designs will be implemented in 28-nanometer processes, so it is important that Synopsys provide designers with high-quality 28-nanometer IP in the timeframe they need to gain a competitive advantage."
AvailabilityThe DesignWare PHY IP for USB 3.0, USB 2.0, USB HSIC, DDR3/2, LPDDR3/2, PCIe 2.0, SATA I/II/III, HDMI 1.4, MIPI M-PHY, MIPI D-PHY, as well as embedded memories, logic libraries and data converters (analog-to-digital converters and digital-to-analog converters) for select 28-nm processes are available now.
The 28-nm DesignWare audio codecs are scheduled to be available to early adopters in Q4 of 2012.
About DesignWare IPSynopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems. To support software development and hardware/software integration of the IP, Synopsys offers drivers, transaction-level models, and prototypes for many of its IP products. Synopsys' HAPS® FPGA-Based Prototyping Solution enables validation of the IP and the SoC in the system context. Synopsys' Virtualizer virtual prototyping tool set allows developers to start the development of software for the IP or the entire SoC significantly earlier compared to traditional methods. With a robust IP development methodology, extensive investment in quality, IP prototyping, software development and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware.
About SynopsysSynopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

ARM and Synopsys Expand Collaboration to Optimize Power and Performance, and Accelerate Design and Verification for ARM Technology-based SoCs

Press release from Synopsys:

ARM and Synopsys Expand Collaboration to Optimize Power and Performance, and Accelerate Design and Verification for ARM Technology-based SoCs

CAMBRIDGE, United Kingdom and MOUNTAIN VIEW, Calif., Aug. 28, 2012 /PRNewswire/ --


Highlights:

• Industry leaders extend collaboration to benefit mutual customers across the broad ARM  partner ecosystem
• Synopsys licenses broad range of energy-efficient, high-performance ARM IP in multi-year agreement
• Collaboration to deliver power and performance optimized methodologies for ARM® Cortex™ processors using Synopsys' Galaxy™ Implementation Platform and ARM Artisan® physical IP and POP™ technology
• Synopsys' next-generation Discovery™ Verification IP (VIP) integrates new tests, checks and verification features to speed verification of AMBA® 4 ACE™-based System-on-Chips (SoCs)

ARM (LON: ARM; Nasdaq: ARMH) and Synopsys, Inc. (Nasdaq: SNPS) have signed a multi-year agreement that expands Synopsys' access to a broad range of ARM intellectual property (IP). The two companies will broaden their collaboration to enable SoC designers to optimize the power and performance of ARM technology-based SoCs with Synopsys Galaxy Implementation Platform and Discovery VIP, while reducing cost and decreasing time to market. Building on previous EDA tools and ARM Cortex-A15 processor license agreements, this new agreement provides Synopsys with access to a range of Cortex processors, including technology needed to implement ARM big.LITTLE™ processing, ARM Artisan physical IP, POP technology optimized for Cortex processor implementation, as well as CoreLink™ interconnect and AMBA 4 ACE system IP.

By expanding their collaboration to include the latest ARM technology, Synopsys will be able to create and deliver optimized tools and methodologies for the implementation and verification of ARM processing subsystems, and ARM will be able to enhance its IP. The ongoing partnership aims to meet demand from designers for SoCs that feature both extreme energy efficiency and high performance. For example, ARM big.LITTLE processing combines Cortex-A15 MPCore™ and Cortex-A7 MPCore processors with ARM CoreLink CCI-400 cache coherent interconnect to allow software to be migrated seamlessly to the optimum processor for each task. This paradigm enables up to 70 percent processor energy savings on common workloads.

"In today's increasingly competitive market environment, optimized solutions from two industry leaders can make a big difference for our partners designing ARM technology-based SoCs by accelerating the design process and driving gains in power and performance," said Simon Segars, executive vice president and general manager, Processor and Physical IP Divisions at ARM. "By providing Synopsys with wider access to industry-leading ARM IP, we are enabling mutual customers to benefit from streamlined design and verification, ultimately, decreasing time to market."

Combining ARM and Synopsys expertise, the optimized implementation flows will use Synopsys Galaxy tools and methodologies as well as ARM Artisan physical IP and POP solutions to better enable designers to produce Cortex-A9, Cortex-A15 and Cortex-A7 processor-based designs faster and with improved performance and power results. This solution is complemented by Synopsys' Virtualizer™ Design Kit (VDK) for ARM big.LITTLE processing, as well as by Synopsys' Discovery Verification IP and Protocol Analyzer for the AMBA 4 ACE specification.

In addition to using the ARM processor-optimized methodologies with Synopsys' Galaxy tools, designers can also use Synopsys' Lynx Design System for additional productivity and predictability through a tapeout-validated, SoC-level implementation flow. Synopsys provides optimized processor implementation training and design assistance to help customers achieve their target performance and power in their chosen semiconductor process technology. Synopsys will also optimize the Discovery Verification Platform for ARM IP. Discovery VIP and Protocol Analyzer integrate additional tests, system monitor checks and other features to accelerate verification of AMBA 4 ACE interconnect-based designs.
"Synopsys tools are used in a significant portion of leading-edge implementations of ARM processor-based SoCs, and our customers are pushing for extreme performance and power efficiency," said Deirdre Hanford, senior vice president, global technical services at Synopsys. "This expanded collaboration enables Synopsys and ARM to deliver the optimized solutions that SoC designers need to meet the power and performance requirements for their ARM-powered designs."

About ARM

ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM by following these links:

• ARM website: http://www.arm.com/
• ARM Connected Community: http://www.arm.com/community/
• ARM Blogs: http://blogs.arm.com/
• ARMFlix on YouTube: http://www.youtube.com/user/ARMflix
• ARM on Twitter:
  • http://twitter.com/ARMMobile
  • http://twitter.com/ARMCommunity
  • http://twitter.com/ARMEmbedded
  • http://twitter.com/ARMSoC
  • http://twitter.com/KeilTools
  • http://twitter.com/ARMMultimedia

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

ARM is a registered trademark of ARM Limited. Synopsys is a registered trademark of Synopsys, Inc. All other trademarks mentioned in this release are the intellectual property of their respective owners.

Synopsys Launches Industry's First Technical Community Site Dedicated to Users of Verification IP

Press release:

Synopsys Launches Industry's First Technical Community Site Dedicated to Users of Verification IP

VIP-Central.org Serves as an Online Resource Connecting Protocol and Verification IP Experts to SoC Verification Engineers

MOUNTAIN VIEW, Calif., Aug. 8, 2012 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the launch of VIP-Central.org, the first industry-wide, technical community site focused on system-on-chip (SoC) verification engineers and users of verification IP (VIP). The site provides a centralized online resource of relevant forums and blogs focused on verification of industry-standard protocols. VIP-Central.org is the go-to source for the latest technical information and discussions on the use of verification IP and advanced verification methodologies to verify protocol-based IP as well as IP integration, SoC sub-systems and full SoCs. VIP-Central.org aggregates information from industry experts across the verification community, providing best practices and ideas for better verification performance, protocol debug, methodology, verification planning, coverage management and ease-of-use.
"As each new SoC adds the next generations of different IP blocks, IP subsystems and frequent releases of new protocols, SoC companies are required to quickly ramp their verification teams to embrace these changes," said Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research. "The launch of VIP-Central.org as a technical resource for protocol-based verification will improve ramp times, act as a repository of knowledge and expertise for designers, and also enable the verification IP experts in the industry to share their best practices with the verification community."
With the increasing number of complex protocols used in SoCs, verification engineers face a tough challenge to quickly acquire the protocol expertise needed to verify a SoC as well as all of its on-chip fabrics and off-chip interfaces. The challenge is made tougher by the frequent release of new and more sophisticated generations of protocols to improve performance, power and quality of service. Verification engineers must complete many tasks requiring both protocol and methodology expertise including developing environments, integrating VIP, using and modifying test sequences, debugging complex protocol results and analyzing coverage data. VIP-Central.org is designed to help engineers quickly understand the intricacies and foibles of each protocol and how to effectively utilize industry-available verification IP to verify these protocols while employing methodologies such as UVM, OVM and VMM.
"VIP-Central.org represents an important milestone for the VIP user community," said Janick Bergeron, verification fellow at Synopsys. "As protocols become more intricate and SoC verification complexity continues to grow, VIP-Central.org offers a community-driven portal to share the learning from our successful customer VIP engagements, and enable exchange of ideas with other VIP experts, users and the entire SoC verification community."
About VIP-Central.org
VIP-Central.org is an industry-wide community site for system-on-chip (SoC) verification engineers and users of verification IP. It provides a centralized online resource of relevant forums and blogs focusing on verification of today's industry-standard protocols. Visit VIP-Central.org online at http://www.vip-central.org/.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.